One-Day Power Delivery System Design Class


Speeding Edge is now offering a one-day power delivery system (PDS) design class as an on-site class. Today´s high-speed designs use a variety of power delivery components and successfully designing a PDS and the PCB into which is incorporated requires a thorough understanding of the overall power delivery system. In addition to reviewing the PDS components currently available; this course examines how to meet the conflicting goals of the PDS system and how to address power plane, impedance and overall system capacitance issues. 

As with the other courses offered by Speeding Edge, the PDS design class is structured to take the student through the entire PDS design process. The class begins with the goals of the PDS design process including how to arrive at a reliable design in the shortest amount of time and at the lowest cost possible with a minimal use of single-source suppliers and specialty components and materials. The course will also examine several real-world PDS designs to further illustrate the goals of the design process.

The materials and examples used in this course are drawn from actual designs of PDS systems in current manufacture. These examples range from subminature disc drives to terabit routers and supercomputers. The design process presented is based on many years of completing designs that are "right the first time". The goal of the course is for students to take the information learned in class and start applying it immediately to their designs-to trouble-shoot existing designs or incorporate into next-generation product iterations.

  • Goals of the PDS process
  • Conflicting demands and goals
  • What do loads look like
  • Getting load I/C data
  • What to do when I/C data is not available
  • Characteristics of PDS components
  • Characteristics of Planes-L, C, R resonances
  • Getting power into and out of planes
  • Combining planes and capacitors
  • Deciding on PDS impedance
  • Making all power rails low impedance
  • Determining types and quantities of capacitors
  • Designing a PCB stackup
  • Where return currents flow
  • How to address four-layer PCBs that have no plane capacitance
  • Capacitance located on die and on package
  • A design process that includes PDS design
  • PDS design tools
  • Simulating and testing the PDS

How This Course Differs From The Speeding Edge Two-Day High Speed PCB and System Design Course:

There is not adequate time in our two-day course to provide a complete treatment of all the topics that need to be addressed to design a stable power delivery system. Specifically, this one-day course provides:

  • A complete treatment of the various capacitor choices including their flaws and benefits
  • A complete treatment of the on-PCB, on-package and on-die PDS issues that are required by today's complex, high-speed ASICs
  • How to determine what loads look like
  • Testing of the PDS to ensure proper operation in the completed PCB

Who Should Take This Course

This course is designed for all the participants in the design process. Among those who will find it valuable are:

  • Design engineers
  • System architects
  • EMC specialists
  • Signal integrity engineers
  • Technicians
  • PCB layout professionals
  • Applications engineers
  • IC designers
  • IC package designers
  • Test engineers
  • Project engineers
  • Design managers
  • Engineering managers


Any engineering professional who works with high speed design will understand the materials presented. No advanced mathematics are required.

Why Take This Course
The speeds and power levels of current and future electronic products have changed to the point where techniques used in the past and commonly described in applications notes do not result in stable power delivery systems. To arrive at successful designs, engineers need to be fluent in the skills involved in designing the complete power delivery system. This one day course covers of all these skills along with many practical examples to provide a starting point for new designs.

Click Here to Download the Course Description

PCB Stackup Design- Optimizing Signal Integrity, Manufacturability and Reliability of a Printed Circuit Board

Successful fabrication of any PCB starts with selecting the right laminate materials and creating a stackup design that works. Today’s high-speed PCBs with their inherent signal integrity and power delivery requirements make it necessary to employ far more discipline in the choice of materials and the arrangement of layers in the stackup. These requirements are outside the skill set of all PCB fabricators.  The objective of this course is to guide the design engineer through the process of evaluating and selecting the right laminate for any given design and then designing a PCB stackup that meets the numerous demands of a complex, multilayer board that works right the first time.

The first portion of this class consists of a one-hour session conducted by Isola Group.Topics that will be addressed include the building blocks available for core and prepeg materials; the impact of material selection; an overview of available materials; what designers should be looking for during the evaluation and selection process and a short tutorial on Isostack, a new web-based stackup tool. and how they are used in various design implementations and what designers should be looking for during the evaluation and selection process.
The second portion of the class, which delves more into the role of laminates in high-speed PCBs as well as how to create a successful stackup design, is conducted by Lee Ritchey. Founder and president of Speeding Edge, he is considered to be one of the industry’s premier authorities on the design and manufacture of high-speed PCB systems. The fast data paths that are pervasive in all PCB products being currently designed make it imperative to be able to design stackups that have predictable and repeatable impedances.

The demands addressed in this portion of the course include:

  • Providing enough signal layers to allow successful routing of all signals to signal integrity rules.
  • Copper thickness in planes and signal layers that meets the conductivity demands of signals and power, and at the same time, be reasonable to manufacture.
  • Accounting for copper roughness and its affect on overall signal path loss.
  • Specifying dielectric materials that are economical to manufacture and are readily available.
  • Specifying glass weave styles to minimize differential signal skew.
  • Dealing with the combined loss from both the dielectric and the copper loss to arrive at an effective loss tangent that accurately predicts overall path losses.
  • Specifying copper surface roughness to ensure repeatable loss from lot to lot and fabricator to fabricator.
  • Show how to document a stackup to ensure all design goals are met with finished PCBs.
  • Providing enough power and ground layers to meet the needs of the power delivery system.
  • Determining dimension trade widths and dielectric thicknesses that allow impedance targets to be met.
  • Ensuring that the spacing between signal layers and their adjacent planes is thin enough to satisfy cross talk needs.
  • Avoiding the use of expensive techniques such as blind and buried vias and build up processing if possible.
  • Providing for prototyping manufacture in one factory or country and production manufacture in another factory or country.

The following topic areas will be covered in this portion of the course:

  • How a typical multilayer PCB is built.
  • Alternative PCB Fabrication Methods.
  • Choosing a fabricator as a design partner.
  • Types of signal layers.
  • Alternate ways to stack layers.
  • Selecting an impedance.
  • Making all signal layers the same impedance.
  • Selecting laminates.
  • Considerations when selecting a laminate system.
  • Obtaining laminate information.
  • How thin should laminate and prepeg be to ensure successful manufacture.
  • Laminate glass weave styles and their effect on differential skew.
  • Selecting the proper copper foil thickness and surface finish.
  • Calculating impedance.
  • Measuring impedance.
  • Impedance test structures.
  • Impedance accuracy.
  • Steps in designing a stackup.
  • Stackup test structurs.
  • Accounting for resin in prepeg flowing into adjacent signal and plane layers.
  • A full stackup drawing.
  • Tools for creating PCB stackups.
  • What about four layer PCBs.

Who should take this course:

This course is designed for all the participants in the design and fabrication process. Among those who will find it valuable are:

  • Design engineers
  • System architects
  • EMC specialists
  • Signal integrity engineers
  • Technicians
  • PCB layout professionals
  • Applications engineers
  • IC designers
  • IC package designers
  • Test engineers
  • Project engineers
  • Design managers
  • Engineering managers


Any engineering professional who works with high speed design will understand the materials presented. No advanced mathematics are required.

Course Materials

The course fee includes a copy of the course slides. A signed course certificate will be prepared for each student.


Lee Ritchey is considered to be one of the industry´s premier authorities on high speed PCB and system design and fabrication. He has participated in the design of more than 4,000 high speed PCBs ranging from PC mother boards and elevator controllers to the backplanes used in terabit routers. He is currently involved in the design of several super computer class products as well as video games and servers of all kinds. The course draws substantially from this real-time experience with state of the art components, fabricators and materials. It also draws heavily on the design of backplanes and daughter boards containing thousands of 2.4, 4.8 and 9.6 GB/S signal paths.

In 2004, Ritchey was a regular columnist for EE Times and he has written many articles on high speed design for trade publications such as EDN, Circuitree and PC Design. He is the author of the books, "Right the First Time, A Practical Handbook on PCB and System Design, Volume 1 and Volume 2,” published by Speeding Edge.

Click Here to Download the Course Description



This one day course is intended to cover all of the technical issues involved in the design of very high speed differential pair signal paths.  This is a thorough treatment of all of the topics that must be considered in order to be successful as the speeds of differential pair signal paths continue to increase.

28Gb/S signaling is already being successfully shipped in high performance servers, routers and switches.  When data rates exceed 5 Gb/S there are a number of areas that need to be managed which were not significant issues at lower data rates.  Among these are the type of glass weave used in laminates, the surface finish on the copper used for signal layers and the loss characteristics of the laminate itself.  Effects of vias and other drilled holes can have a significant effect on signal quality if not properly managed.

This course will draw on more than 30 test PCBs built to determine the properties of new laminate systems as well as to measure the effects of vias, plane crossings and other features that might affect high speed signals.


  • How differential pairs operate
  • Power delivery issues with differential pairs
  • Managing cross talk in differential pairs
  • Signal degradation sources- a real data path will be modeled and signal speed increased
  • Bandwidth requirements for differential pairs
  • How skew affects differential pairs
  • How laminate choices affect skew
  • Managing skew in differential pairs
  • How laminate choice affects loss
  • How choice of copper finish affects loss
  • How processing at fabricators affects loss
  • Routing differential pairs for optimum performance
  • Choosing connectors for high speed differential pairs
  • Connector pin out to minimize unwanted cross talk
  • How vias can affect signal quality
  • When can vias be ignored?
  • How to prevent vias from degrading signal quality
  • Choosing materials that enable good signal quality without over specifying
  • Is a low DK (dielectric constant) material necessary for high speed signaling?
  • Handling high speed differential signals on  twisted pairs 
  • Handling high speed differential pairs on flexible circuits
  • Characteristics of new laminates developed for high speed signaling
  • Adaptive transceivers
  • Equalizing techniques
  • Simulation of high speed data paths
  • Documentation required in order to insure boards containing high speed differential  pairs are properly fabricated


This course is designed for all of the participants in the design process.  Among those who will find this course valuable are:

  • Design Engineers
  • System Architects
  • EMC Specialists
  • Signal Integrity Engineers
  • Technicians
  • PCB Layout Professionals
  • Applications Engineers
  • IC Designers
  • IC Packaging Engineers
  • Test Engineers
  • Project Engineers
  • Design Engineers
  • Engineering Managers


As the speeds of high data rate serial links continues to increase, the margins for error and loss continue to decrease.  In order to manufacture PCBs that perform properly at these ever increasing data rates far more control over materials, manufacturing and layout is necessary.  This course covers each of these crucial areas in enough detail to assure successful first time designs.



It is useful to have completed the two or three day signal integrity course offered by Speeding Edge, but not necessary.  Good engineering training is also valuable, but PCB designers will get valuable information from the course that will enable them to understand why new layout requirements have been added to their tasks.


Each student will receive a binder with all of the class slides in it.  In addition, a CD with a large collection of pertinent articles and technical papers will be provided that will be loaded onto a server accessible to each student for downloading.

Click Here to Download a Course Description